Field of the Disclosure
The present disclosure relates generally to caching in processing systems and more particularly to multilevel cache hierarchies employing a write-back policy.
Description of the Related Art
Processing systems often employ multilevel cache hierarchies to bridge the performance gap between processors and system memory. In cache hierarchies employing a write-back policy with an inclusive scheme or a non-inclusive/non-exclusive scheme, modifying a cache line in a higher level cache (or inner) cache, (e.g., an L1 cache) may result in the invalidation of a copy of that cache line in a lower level (or outer) cache, (e.g., an L2 cache) until the data is written back to the lower level cache. In some cases it may be necessary to maintain the tags associated with the invalidated cache line in the lower level cache, such as for the purposes of cache coherence, resulting in an unused or “dead” cache block with valid tags. In many instances, caches contain mostly dead cache blocks, resulting in inefficient use of the cache hierarchy that can cause unnecessary cache misses, cache re-fetches, lower performance, and higher power consumption.